1. Field of the Invention
Example embodiments of the present invention relate to semiconductor memory devices, for example, a semiconductor memory device including an input/output (I/O) line precharge circuit and method of precharging an I/O line.
2. Description of the Conventional Art
A conventional I/O line must be precharged in order to write and/or read data to/from a memory cell array of a conventional semiconductor memory device. As semiconductor memory devices become more integrated, the number of the I/O lines may be increased. When the number of the I/O lines is increased, power consumption and/or electrical noise may increase.
FIG. 1 is a circuit diagram illustrating a conventional semiconductor memory device including an I/O line driver 10 and a precharge circuit 20. Referring to FIG. 1, the I/O line driver 10 includes drivers DRV1 and DRV2 for driving I/O lines IO<0>and IOB<0>. The drivers DRV1 and DRV2 may include a pull-up transistor and a pull-down transistor, respectively. Each of the pull-up and pull-down transistors may be implemented using NMOS transistors. The precharge circuit 20 may include PMOS transistors M5, M6 and M7, and may be coupled to the I/O lines IO<0> and IOB<0>. When the precharge circuit 20 is activated, the I/O lines IO<0> and IOB<0> may precharge to a higher voltage VDD.
The conventional semiconductor memory device implemented using a semiconductor integrated circuit (IC) may include a plurality of pairs of I/O lines, a plurality of the I/O line drivers 10 and a plurality of the precharge circuits 20. To write data to the semiconductor memory device, an active command signal and a write command signal may be activated. After the write command signal is activated, an I/O line precharge signal PIOPRB_A may be deactivated and a write pulse signal PDT_A may be activated.
Before the write command signal is activated, the PMOS transistors M5, M6 and M7 of the precharge circuit 20 may turn on, and the I/O lines IO<0> and IOB<0> precharge to the voltage VDD. Because the write pulse signal PDT_A is at a logic ‘low’ level (e.g., a logic ‘0’), the NMOS transistors M1 and M2 of the driver DRV1 and the NMOS transistors M3 and M4 of the driver DRV2 turn off. As the write command signal is activated, the PMOS transistors M5, M6 and M7 of the precharge circuit 20 may turn off and the NMOS transistors M1 and M2 of the driver DRV1 and the NMOS transistors M3 and M4 of the driver DRV2 may selectively turn off based on input data DIO<0>. For example, when the input data DIO<0> has a ‘high’ logic level (e.g., a logic ‘1’), the NMOS transistors M1 and M4 may turn off, and the NMOS transistor M2 and M3 may turn on. After all of the input data are written to a selected memory bank, the write command signal may deactivate and the I/O line precharge signal PIOPRB_A may be activated. As a result, the I/O lines IO<0> and IOB<0> may precharge to the voltage VDD. During the write operation, a data mask signal PDMB may activate and transition to a logic ‘low’ level. When the data mask signal PDMB activates, the I/O lines corresponding to each of the memory banks precharge to the voltage VDD, and all of the NMOS transistors M1, M2, M3 and M4 turn off.
Because the precharge circuit 20 of the semiconductor memory device shown in FIG. 1 comprises PMOS transistors M5, M6 and M7, the I/O lines I/O<0> and IOB<0> precharge to the voltage VDD. When the I/O lines I/O<0> and IOB<0> precharge to the voltage VDD, a data write operation may cause unnecessary power consumption and/or an unnecessarily long period required to perform data transition.
Alternatively, the conventional precharge circuit 20 of the semiconductor memory device may comprise NMOS transistors. When the precharge circuit 20 is implemented using the NMOS transistors, the I/O lines IO<0> and IOB<0> precharge to (VDD-Vth) due to a threshold voltage Vth of the NMOS transistor. When the I/O lines I/O<0> and IOB<0> precharge to the lower voltage (VDD-Vth), a voltage level of the I/O lines may swing between (VDD-Vth) and ground or between ground and (VDD-Vth). In this example, the power consumption of the semiconductor memory device may be reduced and/or an operating speed of the semiconductor memory device may improve. However, when the I/O lines I/O<0> and IOB<0> precharge to (VDD-Vth), an I/O sense amplifier may not operate with sufficient stability during the read operation. In addition, or alternatively, the precharge operation of the I/O lines I/O<0> and IOB<0> may not be performed with sufficient stability because of the lower precharge level.